15.3.1.19 PWM Generator x Leading-Edge Blanking Register

Caution should be exercised when modifying this register while PGxCON.ON = 1; unexpected results may occur.

Name:	PGxLEB
Offset:	0x1090, 0x1104, 0x1178, 0x11EC, 0x1260, 0x12D4, 0x1348, 0x13BC


Bit	31	30	29	28	27	26	25	24
	TRGD	TRGC	TRGB	TRGA	PHR	PHF	PLR	PLF
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
					LEB[19:16]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
	LEB[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	LEB[7:4]
Access	R/W	R/W	R/W	R/W
Reset	0	0	0	0

Bit 31 – TRGD PGxTRIGD Kick-Off bit

Value	Description
`1`	PGxTRIGD compare event will trigger LEB duration counter.
`0`	LEB ignores PGxTRIGD compare event.

Bit 30 – TRGC PGxTRIGC Kick-Off bit

Value	Description
`1`	PGxTRIGC compare event will trigger LEB duration counter.
`0`	LEB ignores PGxTRIGC compare event.

Bit 29 – TRGB PGxTRIGB Kick-Off bit

Value	Description
`1`	PGxTRIGB compare event will trigger LEB duration counter.
`0`	LEB ignores PGxTRIGB compare event.

Bit 28 – TRGA PGxTRIGA Kick-Off bit

Value	Description
`1`	PGxTRIGA compare event will trigger LEB duration counter.
`0`	LEB ignores PGxTRIGA compare event.

Bit 27 – PHR PWMx Rising Edge Trigger Enable bit

Value	Description
`1`	Rising edge of PWMx will trigger the LEB duration counter.
`0`	LEB ignores the rising edge of PWMx.

Bit 26 – PHF PWMxH Falling Edge Trigger Enable bit

Value	Description
`1`	Falling edge of PWMx will trigger the LEB duration counter.
`0`	LEB ignores the falling edge of PWMx.

Bit 25 – PLR PWMx Rising Edge Trigger Enable bit

Value	Description
`1`	Rising edge of PWMx will trigger the LEB duration counter.
`0`	LEB ignores the rising edge of PWMx.

Bit 24 – PLF PWMx Falling Edge Trigger Enable bit

Value	Description
`1`	Falling edge of PWMx will trigger the LEB duration counter.
`0`	LEB ignores the falling edge of PWMx.

Bits 19:16 – LEB[19:16] Leading-Edge Blanking Period bits

Bits 15:8 – LEB[15:8] Leading-Edge Blanking Period bits

Bits 7:4 – LEB[7:4] Leading-Edge Blanking Period bits

These bits select the leading edge blanking period. The 4 LSbs of the blanking time are not implemented, providing a blanking resolution of TPWMCLK. The LEB period is (LEB[15:4]+1)*TPWMCLK. The minimum blanking period is 5. Values 0,1,2,3,4 all get LEB period of 5*TPWMCLK.