15.3.1.46 PWM Generator x Event 1 Register

Note:

Caution should be exercised when modifying this bit(s) while PGxCON.ON = 1; unexpected results may occur.
This source can be optionally be used as a PCI input, PCI qualifier, PCI terminator or PCI terminator qualifier.

Name:	APGxEVT1
Offset:	0x1448, 0x14BC, 0x1530, 0x15A4


Bit	31	30	29	28	27	26	25	24
	FLT2IEN	FLT1IEN	CLIEN	FFIEN	SIEN		IEVTSEL[1:0]
Access	R/W	R/W	R/W	R/W	R/W		R/W	R/W
Reset	0	0	0	0	0		0	0


Bit	23	22	21	20	19	18	17	16
	PWMPCI[2:0]			UPDTRG[1:0]		PGTRGSEL[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	DACTREN2	DACTREN1		ADTR1OFS[4:0]
Access	R/W	R/W		R/W	R/W	R/W	R/W	R/W
Reset	0	0		0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ADTR1PS[4:0]					ADTR1EN3	ADTR1EN2	ADTR1EN1
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 31 – FLT2IEN PCI Fault 2 Interrupt Enable bit

Note: An interrupt is only generated on the rising edge of the PCI Fault active signal.

Value	Description
`1`	Fault interrupt is enabled.
`0`	Fault interrupt is disabled.

Bit 30 – FLT1IEN PCI Fault 1 Interrupt Enable bit

Note: An interrupt is only generated on the rising edge of the PCI Fault active signal.

Value	Description
`1`	Fault interrupt is enabled.
`0`	Fault interrupt is disabled.

Bit 29 – CLIEN PCI Current Limit Interrupt Enable bit

Note: An interrupt is only generated on the rising edge of the PCI current limit active signal.

Value	Description
`1`	Current limit interrupt is enabled.
`0`	Current limit interrupt is disabled.

Bit 28 – FFIEN PCI Feed-Forward Interrupt Enable bit

Note: An interrupt is only generated on the rising edge of the PCI feed-forward active signal.

Value	Description
`1`	Feed-forward interrupt is enabled.
`0`	Feed-forward interrupt is disabled.

Bit 27 – SIEN PCI Sync Interrupt Enable bit

Note: An interrupt is only generated on the rising edge of the PCI Sync active signal.

Value	Description
`1`	Sync interrupt is enabled.
`0`	Sync interrupt is disabled.

Bits 25:24 – IEVTSEL[1:0] Interrupt Event Selection bits⁽¹⁾

Value	Description
`11`	Time base interrupts are disabled (Sync, Fault, current limit and feed-forward events can be independently enabled).
`10`	Interrupts CPU at ADC Trigger 1 event.
`01`	Interrupts CPU at TRIGA compare event.
`00`	Interrupts CPU at EOC.

Bits 23:21 – PWMPCI[2:0] PWM PCI Source Selection bits⁽²⁾

Bits 20:19 – UPDTRG[1:0] Update Trigger Select bits⁽¹⁾

Value	Description
`11`	A write of the PGxTRIGA register automatically sets the UPDREQ bit.
`10`	A write of the PGxPHASE register automatically sets the UPDREQ bit.
`01`	A write of the PGxDC register automatically sets the UPDREQ bit.
`00`	User must set the UPDREQ bit (PGxSTAT[3]) manually.

Bits 18:16 – PGTRGSEL[2:0] PWM Generator Trigger Output Selection bits⁽¹⁾

Note: These events are derived from the internal PWM Generator time base comparison events.

Value	Description
`111`	Reserved
`110`	Reserved
`101`	Reserved
`100`	Reserved
`011`	PGxTRIGC compare event is the PWM Generator trigger.
`010`	PGxTRIGB compare event is the PWM Generator trigger.
`001`	PGxTRIGA compare event is the PWM Generator trigger.
`000`	EOC event is the PWM Generator trigger.

Bit 15 – DACTREN2 DAC Trigger Source is PGxTRIGE Compare Event Enable bit

Value	Description
`1`	PGxTRIGE register compare event enabled as trigger source for DAC trigger.
`0`	PGxTRIGE register compare event disabled as trigger source for DAC trigger.

Bit 14 – DACTREN1 DAC Trigger Source is PGxTRIGD Compare Event Enable bit

Value	Description
`1`	PGxTRIGD register compare event enabled as trigger source for DAC trigger.
`0`	PGxTRIGD register compare event disabled as trigger source for DAC trigger.

Bits 12:8 – ADTR1OFS[4:0] ADC Trigger 1 Offset Selection bits⁽¹⁾

Value	Description
`11111`	Offset by 31 trigger events
`. . .`	`. . .`
`00010`	Offset by 2 trigger events
`00001`	Offset by 1 trigger event
`00000`	No offset

Bits 7:3 – ADTR1PS[4:0] ADC Trigger 1 Postscaler Selection bits⁽¹⁾

Value	Description
`11111`	1:32
`. . .`	`. . .`
`00010`	1:3
`00001`	1:2
`00000`	1:1

Bit 2 – ADTR1EN3 ADC Trigger 1 Source is PGxTRIGC Compare Event Enable bit⁽¹⁾

Value	Description
`1`	PGxTRIGC register compare event is enabled as trigger source for ADC Trigger 2.
`0`	PGxTRIGC register compare event is disabled as trigger source for ADC Trigger 2.

Bit 1 – ADTR1EN2 ADC Trigger 1 Source is PGxTRIGB Compare Event Enable bit⁽¹⁾

Value	Description
`1`	PGxTRIGB register compare event is enabled as trigger source for ADC Trigger 2.
`0`	PGxTRIGB register compare event is disabled as trigger source for ADC Trigger 2.

Bit 0 – ADTR1EN1 ADC Trigger 1 Source is PGxTRIGA Compare Event Enable bit⁽¹⁾

Value	Description
`1`	PGxTRIGA register compare event is enabled as trigger source for ADC Trigger 2.
`0`	PGxTRIGA register compare event is disabled as trigger source for ADC Trigger 2.

15.3.1.46 PWM Generator x Event 1 Register

Bit 31 – FLT2IEN PCI Fault 2 Interrupt Enable bit

Bit 30 – FLT1IEN PCI Fault 1 Interrupt Enable bit

Bit 29 – CLIEN PCI Current Limit Interrupt Enable bit

Bit 28 – FFIEN PCI Feed-Forward Interrupt Enable bit

Bit 27 – SIEN PCI Sync Interrupt Enable bit

Bits 25:24 – IEVTSEL[1:0] Interrupt Event Selection bits(1)

Bits 23:21 – PWMPCI[2:0] PWM PCI Source Selection bits(2)

Bits 20:19 – UPDTRG[1:0] Update Trigger Select bits(1)

Bits 18:16 – PGTRGSEL[2:0] PWM Generator Trigger Output Selection bits(1)

Bit 15 – DACTREN2 DAC Trigger Source is PGxTRIGE Compare Event Enable bit

Bit 14 – DACTREN1 DAC Trigger Source is PGxTRIGD Compare Event Enable bit

Bits 12:8 – ADTR1OFS[4:0] ADC Trigger 1 Offset Selection bits(1)

Bits 7:3 – ADTR1PS[4:0] ADC Trigger 1 Postscaler Selection bits(1)

Bit 2 – ADTR1EN3 ADC Trigger 1 Source is PGxTRIGC Compare Event Enable bit(1)

Bit 1 – ADTR1EN2 ADC Trigger 1 Source is PGxTRIGB Compare Event Enable bit(1)

Bit 0 – ADTR1EN1 ADC Trigger 1 Source is PGxTRIGA Compare Event Enable bit(1)