15.3.1.4 Master Phase Register

Name:	MPHASE
Offset:	0x100C


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					MPHASE[19:16]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
	MPHASE[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	MPHASE[7:4]				Reserved[3:0]
Access	R/W	R/W	R/W	R/W	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bits 19:16 – MPHASE[19:16] Master Phase Register bits

This register holds the phase offset value that can be shared by multiple PWM Generators.

Bits 15:8 – MPHASE[15:8] Master Phase Register bits

This register holds the phase offset value that can be shared by multiple PWM Generators.

Bits 7:4 – MPHASE[7:4] Master Phase Register bits

This register holds the phase offset value that can be shared by multiple PWM Generators.

Bits 3:0 – Reserved[3:0]

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