15.3.1.61 PWM Generator x Duty Cycle Adjustment Register
Note: This register cannot be modified while PGxSTAT.UPDATE =
1.
| Name: | APGxDCA |
| Offset: | 0x1484, 0x14F8, 0x156C, 0x15E0 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DCA[11:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DCA[7:4] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 11:8 – DCA[11:8]
Bits 7:4 – DCA[7:4] PWM Generator x Duty Cycle Adjustment Value bits
Depending on the state of the selected PCI source, the PGxDCA value will be added to the value in the PGxDC register to create the effective duty cycle. When the PCI source is active, PGxDCA is added.