15.3.1.47 PWM Generator x Event 2 Register

Note:

Caution should be exercised when modifying this bit(s) while PGxCON.ON = 1; unexpected results may occur.
This source can be optionally be used as a PCI input, PCI qualifier, PCI terminator or PCI terminator qualifier.

Name:	APGxEVT2
Offset:	0x144C, 0x14C0, 0x1534, 0x15A8


Bit	31	30	29	28	27	26	25	24
				CAPTROFS[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	CAPTRPS[4:0]
Access	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
				ADTR2OFS[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ADTR2PS[4:0]					ADTR2EN3	ADTR2EN2	ADTR2EN1
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 28:24 – CAPTROFS[4:0] Timebase capture to Trigger Offset Selection bits

Value	Description
11111	Offset by 31 trigger events
...
00010	Offset by 2 trigger events
00001	Offset by 1 trigger event
00000	No offset

Bits 23:19 – CAPTRPS[4:0] Timebase capture to Trigger Post Scaler Selection bits

Value	Description
11111	1:32
...
00010	1:3
00001	1:2
00000	1:1

Bits 12:8 – ADTR2OFS[4:0] ADC Trigger 2 Offset Selection bits⁽¹⁾

Value	Description
`11111`	Offset by 31 trigger events
`. . .`	`. . .`
`00010`	Offset by 2 trigger events
`00001`	Offset by 1 trigger event
`00000`	No offset

Bits 7:3 – ADTR2PS[4:0] ADC Trigger 2 Postscaler Selection bits⁽¹⁾

Value	Description
`11111`	1:32
`. . .`	`. . .`
`00010`	1:3
`00001`	1:2
`00000`	1:1

Bit 2 – ADTR2EN3 ADC Trigger 2 Source is PGxTRIGC Compare Event Enable bit⁽¹⁾

Value	Description
`1`	PGxTRIGC register compare event is enabled as trigger source for ADC Trigger 1.
`0`	PGxTRIGC register compare event is disabled as trigger source for ADC Trigger 1.

Bit 1 – ADTR2EN2 ADC Trigger 2 Source is PGxTRIGB Compare Event Enable bit⁽¹⁾

Value	Description
`1`	PGxTRIGB register compare event is enabled as trigger source for ADC Trigger 1.
`0`	PGxTRIGB register compare event is disabled as trigger source for ADC Trigger 1.

Bit 0 – ADTR2EN1 ADC Trigger 2 Source is PGxTRIGA Compare Event Enable bit⁽¹⁾

Value	Description
`1`	PGxTRIGA register compare event is enabled as trigger source for ADC Trigger 1.
`0`	PGxTRIGA register compare event is disabled as trigger source for ADC Trigger 1.

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