15.3.1.45 PWM Generator x I/O Control 2 Register
- This bit(s) cannot be modified while PGxCON.ON = 1.
- This bit(s) cannot be modified while PCLKCON.LOCK = 1. Otherwise, caution should be exercised when modifying this bit when PGxCON.ON = 1; unexpected results may occur.
- This bit(s) cannot be modified while UPDATE = 1.
- Caution should be exercised when modifying this bit(s) while PGxCON.ON = 1; unexpected results may occur.
| Name: | APGxIOCON2 |
| Offset: | 0x1444, 0x14B8, 0x152C, 0x15A0 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CLMOD | OVRENH | OVRENL | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| OVRDAT[1:0] | OSYNC[1:0] | FLT2DAT[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLT1DAT[1:0] | CLDAT[1:0] | FFDAT[1:0] | DBDAT[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 23 – CLMOD Current Limit Mode Select bit
| Value | Description |
|---|---|
1 |
If PCI current limit is active, then the PWMxH and PWMxL output signals are inverted (bit flipping), and the CLDAT[1:0] bits are not used |
0 |
If PCI current limit is active, then the CLDAT[1:0] bits define the PWM output levels |
Bit 21 – OVRENH User Override Enable for PWMxH Pin bit
| Value | Description |
|---|---|
1 |
OVRDAT[1] provides data for output on the PWMxH pin |
0 |
PWM Generator provides data for the PWMxH pin |
Bit 20 – OVRENL User Override Enable for PWMxL Pin bit
| Value | Description |
|---|---|
1 |
OVRDAT[0] provides data for output on the PWMxL pin |
0 |
PWM Generator provides data for the PWMxL pin |
Bits 13:12 – OVRDAT[1:0] Data for PWMxH/PWMxL Pins if Override is Enabled bits
| Description |
|---|
|
If OVRENH = |
|
If OVRENL = |
Bits 11:10 – OSYNC[1:0] User Output Override Synchronization Control bits
| Value | Description |
|---|---|
11 |
User output
overrides via the SWAP, OVRENL/H, and OVRDAT[1:0] bits are synchronized to the
data buffer update of the selected PWM mode. This makes this setting equivalent to
setting 10 when UPDMOD[2:0] = 000 with UPDREQ
properly set manually |
10 |
User output overrides via the SWAP, OVRENL/H and OVRDAT[1:0] bits occur when specified by the UPMOD[2:0] bits in the PGxCON register |
01 |
User output overrides via the SWAP, OVRENL/H and OVRDAT[1:0] bits occur immediately (as soon as possible) |
00 |
User output overrides via the SWAP, OVRENL/H and OVRDAT[1:0] bits are synchronized to the local PWM time base (next start of cycle) |
Bits 9:8 – FLT2DAT[1:0] Data for PWMxH/PWMxL Pins if FLT Event is Active bits
| Description |
|---|
|
If Fault is active, then FLTDAT[1] provides data for PWMxH. |
|
If Fault is active, then FLTDAT[0] provides data for PWMxL. |
Bits 7:6 – FLT1DAT[1:0] Data for PWMxH/PWMxL Pins if FLT Event is Active bits
| Description |
|---|
|
If Fault is active, then FLTDAT[1] provides data for PWMxH. |
|
If Fault is active, then FLTDAT[0] provides data for PWMxL. |
Bits 5:4 – CLDAT[1:0] Data for PWMxH/PWMxL Pins if CLMT Event is Active bits
| Description |
|---|
|
If current limit is active, then CLDAT[1] provides data for PWMxH. |
|
If current limit is active, then CLDAT[0] provides data for PWMxL. |
Bits 3:2 – FFDAT[1:0] Data for PWMxH/PWMxL Pins if Feed-Forward Event is Active bits
| Description |
|---|
|
If feed-forward is active, then FFDAT[1] provides data for PWMxH. |
|
If feed-forward is active, then FFDAT[0] provides data for PWMxL. |
Bits 1:0 – DBDAT[1:0] Data for PWMxH/PWMxL Pins if Debug Mode is Active bits
| Description |
|---|
|
If Debug mode is active and PTFRZ = |
|
If Debug mode is active and PTFRZ = |