15.3.1.64 PWM Generator x Trigger B Register
Note: This register cannot be modified while PGxSTAT.UPDATE =
1.
| Name: | APGxTRIGB |
| Offset: | 0x1490, 0x1504, 0x1578, 0x15EC |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CAHALF | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TRIGB[19:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TRIGB[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRIGB[7:4] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 31 – CAHALF Specifies where the trigger compare time occurs
| Value | Description |
|---|---|
1 |
The second phase of the center-aligned period |
0 |
The first phase of the center-aligned period |