15.3.1.13 PWM Generator x I/O Control 1 Register

Note:
  1. This bit(s) cannot be modified while PGxCON.ON = 1.
  2. This bit(s) cannot be modified while PCLKCON.LOCK = 1. Otherwise, caution should be exercised when modifying this bit when PGxCON.ON = 1; unexpected results may occur.
  3. This bit(s) cannot be modified while UPDATE = 1.
  4. Caution should be exercised when modifying this bit(s) while PGxCON.ON = 1; unexpected results may occur.
  5. Updating SWAP on the fly is discouraged as it may cause the outputs to become unsettled.
Name: PGxIOCON1
Offset: 0x1058, 0x10CC, 0x1140, 0x11B4, 0x1228, 0x129C, 0x1310, 0x1384

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 CAPENCAPSRC[2:0]CAPTREN CAPTRSEL[1:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 15141312111098 
     SWAPFORCEONPPSENDTCMPSEL 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
   PMOD[1:0]PENHPENLPOLHPOLL 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 23 – CAPEN Capture Point Enable bit

ValueDescription
1 CaptureTrigger Point is enabled for this register set.
0 CaptureTrigger Point is not enabled for this register set.

Bits 22:20 – CAPSRC[2:0] Time Base Capture Source Selection bits

Note: A capture may be initiated in software at any time by writing a ‘1’ to PGxCAP[0].
ValueDescription
111

Reserved
110

Reserved
101

Capture timebase value at assertion of selected PCI Fault 2 signal.
100

Capture time base value at assertion of selected PCI Fault1 signal.
011

Capture time base value at assertion of selected PCI Current Limit signal.
010

Capture time base value at assertion of selected PCI Feed-Forward signal.
001

Capture time base value at assertion of selected PCI Sync signal.
000

No hardware source selected for time base capture – software only.

Bit 19 – CAPTREN Timebase Capture to Trigger Enable bit

ValueDescription
1 Timebase capture to trigger enabled, trigger value calculated and stored in the selected trigger register per CAPTRSEL[2:0].
0 Timebase capture to trigger disabled.

Bits 17:16 – CAPTRSEL[1:0] Timebase Capture Trigger Register Selection bits

ValueDescription
11 PGxTRIGF selected to store the 50% timebase captured value when enabled.
10 PGxTRIGE selected to store the 50% timebase captured value when enabled.
01 PGxTRIGD selected to store the 50% timebase captured value when enabled.
00 PGxTRIGC selected to store the 50% timebase captured value when enabled.

Bit 11 – SWAP Swap PWM Signals to PWMxH and PWMxL Device Pins bit

ValueDescription
1

The PWMxH signal is connected to the PWMxL pin and the PWMxL signal is connected to the PWMxH pin.
0

PWMxH/L signals are mapped to their respective pins.

Bit 10 – FORCEON Force On Select bit

ValueDescription
1 Active override happens immediately without taking the dead time into account.
0 Active override happens after taking the dead time into account.

Bit 9 – PPSEN Peripheral Pin Select Enable bit

ValueDescription
1 Peripheral pin select enabled.
0 Peripheral pin select disabled, as a result, PWM outputs are hard-mapped to pins.

Bit 8 – DTCMPSEL Dead-Time Compensation Select bit

ValueDescription
1

Dead-time compensation is controlled by PCI feed-forward limit logic.
0

Dead-time compensation is controlled by PCI Sync logic.

Bits 5:4 – PMOD[1:0] PWM Generator Output Mode Selection bits

ValueDescription
11

Reserved
10

PWM Generator outputs operate in Push-Pull mode.
01

PWM Generator outputs operate in Independent mode.
00

PWM Generator outputs operate in Complementary mode.

Bit 3 – PENH PWMxH Output Port Enable bit

ValueDescription
1

PWM Generator controls the PWMxH output pin.
0

PWM Generator does not control the PWMxH output pin.

Bit 2 – PENL  PWMxL Output Port Enable bit(2)

ValueDescription
1

PWM Generator controls the PWMxL output pin.
0

PWM Generator does not control the PWMxL output pin.

Bit 1 – POLH PWMxH Output Polarity bit

ValueDescription
1

Output pin is active-low.
0

Output pin is active-high.

Bit 0 – POLL PWMxL Output Polarity bit

ValueDescription
1

Output pin is active-low
0

Output pin is active-high