15.3.1.18 PWM PCI 2⁽¹⁾

Note:

y = F1, F2, CL, FF, or S.

Name:	PGxyPCI2
Offset:	0x106C, 0x10E0, 0x1154, 0x11C8, 0x123C, 0x12B0, 0x1324, 0x1398


Bit	31	30	29	28	27	26	25	24
	PSS[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	PSS[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	PSS[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PSS[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – PSS[31:0] PCI Source Selection bits

Refer to Table 15-3 for device-specific PSS bit information.