15.3.1.17 PWM Generator y PCI 1


Bit	31	30	29	28	27	26	25	24
	BPEN	SWTERM	PSYNC	PPS	TERMPS	ACP[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	SWPCI	SWPCIM[1:0]		LATMOD	TQPS	TQSS[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	TSYNCDIS	TERM[2:0]			AQPS	AQSS[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	BPSEL[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 31 – BPEN PCI Bypass Enable bit

Value	Description
`1`	PCI function is enabled and local PCI logic is bypassed; PWM Generator will be controlled by PCI function in the PWM Generator selected by the BPSEL[2:0] bits.
`0`	PCI function is not bypassed.

Bit 30 – SWTERM PCI Software Termination bit

A write of ‘1’ to this location will produce a termination event. This bit location always reads as ‘0’.

Bit 29 – PSYNC PCI Synchronization Control bit

Value	Description
`1`	PCI source is synchronized to PWM EOC.
`0`	PCI source is not synchronized to PWM EOC.

Bit 28 – PPS PCI Polarity Select bit

Value	Description
`1`	Inverted
`0`	Not inverted

Bit 27 – TERMPS PCI Termination Polarity Select bit

Note: This bit has no effect when the SWTERM control bit is used as the PCI Termination Event or if TERM[2:0] < ‘101’.

Value	Description
`1`	Inverted
`0`	Not inverted

Bits 26:24 – ACP[2:0] PCI Acceptance Criteria Selection bits

Note: Do not use this selection when the TERM[2:0] bits (PGxyPCI1[14:12]) are set to auto-termination.

Value	Description
111	Qualifier Latched Any Edge (setting 101, below, with PCI/Qualifier inputs swapped)
110	Qualifier Latched Rising Edge (setting 100, below, with the PCI/Qualifier inputs swapped)
101	Latched any edge
100	Latched rising edge
011	Latched
010	Any edge
001	Rising edge
000	Level-sensitive

Bit 23 – SWPCI Software PCI Control bit

Value	Description
`1`	Drives a ‘`1`’ to PCI logic assigned to by the SWPCIM[1:0] control bits.
`0`	Drives a ‘`0`’ to PCI logic assigned to by the SWPCIM[1:0] control bits.

Bits 22:21 – SWPCIM[1:0] Software PCI Control Mode bits

Value	Description
`11`	Reserved
`10`	SWPCI bit is assigned to termination qualifier logic.
`01`	SWPCI bit is assigned to acceptance qualifier logic.
`00`	SWPCI bit is assigned to PCI acceptance logic.

Bit 20 – LATMOD PCI SR Latch Mode bit

Value	Description
`1`	SR latch is Reset-dominant in Latched Acceptance modes.
`0`	SR latch is set-dominant in Latched Acceptance modes.

Bit 19 – TQPS Termination Qualifier Polarity Select bit

Value	Description
`1`	Inverted
`0`	Not inverted

Bits 18:16 – TQSS[2:0] Termination Qualifier Source Selection bits

Note: Polarity control bit, TQPS, has no effect on these selections.

Value	Description
`111`	SWPCI control bit only (qualifier forced to ‘`1`’)
`110`	Selects PCI Source #9
`101`	Selects PCI Source #8
`100`	Selects PCI Source #1 (PWM Generator output selected by the PWMPCI[2:0] bits)
`011`	PWM Generator is triggered.
`010`	LEB is active.
`001`	Duty cycle is active (base PWM Generator signal).
`000`	No termination qualifier used (qualifier forced to ‘`1`’)

Bit 15 – TSYNCDIS Termination Synchronization Disable bit

Value	Description
`1`	Termination of latched PCI occurs immediately.
`0`	Termination of latched PCI occurs at PWM EOC.

Bits 14:12 – TERM[2:0] Termination Event Selection bits

Note: Do not use this selection when the ACP[2:0] bits (PGxyPCI1[26:24]) are set for latched on any edge.

Value	Description
`111`	Selects PCI Source #9
`110`	Selects PCI Source #8
`101`	Selects PCI Source #1 (PWM Generator output selected by the PWMPCI[2:0] bits)
`100`	PGxTRIGC trigger event
`011`	PGxTRIGB trigger event
`010`	PGxTRIGA trigger event
`001`	Auto-Terminate: Terminate when PCI source transitions from active to inactive⁽²⁾.
`000`	Manual Terminate: Terminate on a write of ‘`1`’ to the SWTERM bit location.

Bit 11 – AQPS Acceptance Qualifier Polarity Select bit

Value	Description
`1`	Inverted
`0`	Not inverted

Bits 10:8 – AQSS[2:0] Acceptance Qualifier Source Selection bits

Value	Description
`111`	SWPCI control bit only (qualifier forced to ‘`0`’)
`110`	Selects PCI Source #9
`101`	Selects PCI Source #8
`100`	Selects PCI Source #1 (PWM Generator output selected by the PWMPCI[2:0] bits)
`011`	PWM Generator is triggered.
`010`	LEB is active.
`001`	Duty cycle is active (base PWM Generator signal).
`000`	No acceptance qualifier is used (qualifier forced to ‘`1`’).

Bits 7:0 – BPSEL[7:0] PCI Bypass Source Selection bits^(1,2)

BPSEL[7] = PCI control sourced from PWM Generator 8 PCI logic when BPEN = 1

BPSEL[6] = PCI control sourced from PWM Generator 7 PCI logic when BPEN = 1

BPSEL[5] = PCI control sourced from PWM Generator 6 PCI logic when BPEN = 1

BPSEL[4] = PCI control sourced from PWM Generator 5 PCI logic when BPEN = 1

BPSEL[3] = PCI control sourced from PWM Generator 4 PCI logic when BPEN = 1

BPSEL[2] = PCI control sourced from PWM Generator 3 PCI logic when BPEN = 1

BPSEL[1] = PCI control sourced from PWM Generator 2 PCI logic when BPEN = 1

BPSEL[0] = PCI control sourced from PWM Generator 1 PCI logic when BPEN = 1

Note:

If more than one bit is set, the selected bypass sources are OR’ed together.
Setting PCI control sourced from own generation is not allowed.

Name:	PGxyPCI1
Offset:	0x1068, 0x10DC, 0x1150, 0x11C4, 0x1238, 0x12AC, 0x1320, 0x1394