15.3.1.12 PWM Generator x Status Register


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
				SEVT	FLT2EVT	FLT1EVT	CLEVT	FFEVT
Access				HS/C	HS/C	HS/C	HS/C	HS/C
Reset				0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
			CAPTR	SACT	FLT2ACT	FLT1ACT	CLACT	FFACT
Access			R	R	R	R	R	R
Reset			0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TRSET	TRCLR	CAP	UPDATE	UPDREQ	STEER	CAHALF	TRIG
Access	W	W	R/HS	R	W	R	R	R
Reset	0	0	0	0	0	0	0	0

Bit 20 – SEVT PCI Sync Event bit

Value	Description
`1`	A PCI Sync event has occurred (rising edge on PCI Sync output or PCI Sync output is high when module is enabled).
`0`	No PCI Sync event has occurred.

Bit 19 – FLT2EVT PCI Fault 2 Active Status bit

Value	Description
`1`	A Fault event has occurred (rising edge on PCI Fault output or PCI Fault output is high when module is enabled).
`0`	No Fault event has occurred.

Bit 18 – FLT1EVT PCI Fault 2 Active Status bit

Value	Description
`1`	A Fault event has occurred (rising edge on PCI Fault output or PCI Fault output is high when module is enabled).
`0`	No Fault event has occurred.

Bit 17 – CLEVT PCI Current Limit Status bit

Value	Description
`1`	A PCI current limit event has occurred (rising edge on PCI current limit output or PCI current limit output is high when module is enabled).
`0`	No PCI current limit event has occurred.

Bit 16 – FFEVT PCI Feed-Forward Active Status bit

Value	Description
`1`	A PCI feed-forward event has occurred (the rising edge on the PCI feed-forward output or PCI feed-forward output is high when module is enabled).
`0`	No PCI feed-forward event has occurred.

Bit 13 – CAPTR Capture Status bit

Value	Description
`1`
`0`

Bit 12 – SACT PCI Sync Status bit

Value	Description
`1`	PCI Sync output is active.
`0`	PCI Sync output is inactive.

Bit 11 – FLT2ACT PCI Fault 2 Active Status bit

Value	Description
`1`	PCI Fault output is active.
`0`	PCI Fault output is inactive.

Bit 10 – FLT1ACT PCI Fault 1 Active Status bit

Value	Description
`1`	PCI Fault output is active.
`0`	PCI Fault output is inactive.

Bit 9 – CLACT PCI Current Limit Status bit

Value	Description
`1`	PCI current limit output is active.
`0`	PCI current limit output is inactive.

Bit 8 – FFACT PCI Feed-Forward Active Status bit

Value	Description
`1`	PCI feed-forward output is active.
`0`	PCI feed-forward output is inactive.

Bit 7 – TRSET PWM Generator Software Trigger Set bit

User software writes a ‘1’ to this bit location to trigger a PWM Generator cycle. The bit location always reads as ‘0’. The TRIG bit will indicate ‘1’ when the PWM Generator is triggered.

Bit 6 – TRCLR PWM Generator Software Trigger Clear bit

User software writes a ‘1’ to this bit location to stop a PWM Generator cycle. The bit location always reads as ‘0’. The TRIG bit will indicate ‘0’ when the PWM Generator is not triggered.

Bit 5 – CAP PGxCAP Status bit

Value	Description
`1`	PWM Generator time base value has been captured in PGxCAP.
`0`	No capture has occurred.

Bit 4 – UPDATE PWM Data Register Update Status/Control bit

Value	Description
`1`	PWM Data register update is pending – user Data registers are not writable.
`0`	No PWM Data register update is pending.

Bit 3 – UPDREQ PWM Data Register Update Request bit

User software writes a ‘1’ to this bit location to request a PWM Data register update. The bit location always reads as ‘0’. The UPDATE status bit will indicate a ‘1’ when an update is pending.

Bit 2 – STEER Output Steering Status (Push-Pull Output mode only) bit

Value	Description
`1`	PWM Generator is in 2nd cycle of Push-Pull mode.
`0`	PWM Generator is in 1st cycle of Push-Pull mode.

Bit 1 – CAHALF Half Cycle Status (Center-Aligned modes only) bit

Value	Description
`1`	PWM Generator is in 2nd half of time base cycle.
`0`	PWM Generator is in 1st half of time base cycle.

Bit 0 – TRIG Trigger Status bit

Value	Description
`1`	PWM Generator is triggered and PWM cycle is in progress.
`0`	No PWM cycle is in progress.

Name:	PGxSTAT
Offset:	0x1054, 0x10C8, 0x113C, 0x11B0, 0x1224, 0x1298, 0x130C, 0x1380