15.3.1.11 PWM Generator x Control Register
- This bit(s) cannot be modified while PGxCON.ON = 1.
- This bit(s) cannot be modified while PCLKCON.LOCK = 1. Otherwise, caution should be exercised when modifying this bit when PGxCON.ON = 1; unexpected results may occur.
- These bits cannot be modified while UPDATE = 1.
- Caution should be exercised when modifying this bit(s) while PGxCON.ON = 1; unexpected results may occur.
- The PCI selected Sync signal is always available to be OR’d with the selected SOC signal per the SOCS[3:0] bits if the PCI Sync function is enabled.
- The source selected by the SOCS[3:0] bits MUST operate from the same clock source as the local PWM Generator. If not, the source must be routed through the PCI Sync logic so the trigger signal may be synchronized to the PWM Generator clock domain.
- PWM Generators are grouped into groups of four: PG1-PG4 and PG5-PG8, if available. Any generator within a group of four may be used to trigger another generator within the same group.
| Name: | PGxCON |
| Offset: | 0x1050, 0x10C4, 0x1138, 0x11AC, 0x1220, 0x1294, 0x1308, 0x137C |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MDCSEL | MPERSEL | MPHSEL | MSTEN | UPDMOD[2:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TRGMOD[1:0] | SOCS[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | FRZ | TRGCNT[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HREN | CLKSEL[1:0] | MODSEL[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 31 – MDCSEL Master Duty Cycle Register Select bit(4)
| Value | Description |
|---|---|
1 |
PWM Generator uses MDC register, |
0 |
PWM Generator uses PGxDC register, |
Bit 30 – MPERSEL Master Period Register Select bit(4)
| Value | Description |
|---|---|
1 |
PWM Generator uses MPER register. |
0 |
PWM Generator uses PGxPER register. |
Bit 29 – MPHSEL Master Phase Register Select bit(4)
| Value | Description |
|---|---|
1 |
PWM Generator uses MPHASE register. |
0 |
PWM Generator uses PGxPHASE register. |
Bit 27 – MSTEN Master Update Enable bit(4)
| Value | Description |
|---|---|
1 |
PWM Generator broadcasts software set of UPDREQ control bit and EOC signal to other PWM Generators. |
0 |
PWM Generator does not broadcast UPDREQ status bit state or EOC signal. |
Bits 26:24 – UPDMOD[2:0] PWM Buffer Update Mode Selection bits
See Table 15-10 for details.
Bits 23:22 – TRGMOD[1:0] PWM Generator x Trigger Mode Selection bits(4)
| Value | Description |
|---|---|
| 11 | Reserved |
| 10 | Reserved |
| 01 | PWM Generator operates in Retriggerable mode. |
| 00 | PWM Generator operates in Single Trigger mode. |
Bits 19:16 – SOCS[3:0] Start-of-Cycle Selection bits(4,5,6,7)
| Value | Description |
|---|---|
1111 |
TRIG bit or PCI Sync function only (no hardware trigger source selected). |
1110 -
0101 |
Reserved |
1000 |
PWM8 PG Trigger output selected by PG8 PGTRGSEL[2:0] bits (PG8EVT[2:0]). |
0111 |
PWM7 PG Trigger output selected by PG7 PGTRGSEL[2:0] bits (PG7EVT[2:0]). |
0110 |
PWM6 PG Trigger output selected by PG6 PGTRGSEL[2:0] bits (PG6EVT[2:0]). |
0101 |
PWM5 PG Trigger output selected by PG5 PGTRGSEL[2:0] bits (PG5EVT[2:0]). |
0100 |
PWM4 PG Trigger output selected by PG4 PGTRGSEL[2:0] bits (PG4EVT[2:0]). |
0011 |
PWM3 PG Trigger output selected by PG3 PGTRGSEL[2:0] bits (PG3EVT[2:0]). |
0010 |
PWM2 PG Trigger output selected by PG2 PGTRGSEL[2:0] bits (PG2EVT[2:0]). |
0001 |
PWM1 PG Trigger output selected by PG1 PGTRGSEL[2:0] bits (PG1EVT[2:0]). |
0000 |
Local EOC - PWM Generator is self-triggered. |
Bit 15 – ON PWM Generator x Enable bit(1)
| Value | Description |
|---|---|
1 |
PWM Generator is enabled. |
0 |
PWM Generator is not enabled. |
Bit 14 – FRZ PGx Freeze bit
| Value | Description |
|---|---|
1 |
PGx stops operation in Debug mode. |
0 |
PGx continues operation in Debug mode. |
Bits 10:8 – TRGCNT[2:0] PWM Generator x Trigger Count Select bits(1)
| Value | Description |
|---|---|
111 |
PWM Generator produces 8 PWM cycles after triggered. |
110 |
PWM Generator produces 7 PWM cycles after triggered. |
101 |
PWM Generator produces 6 PWM cycles after triggered. |
100 |
PWM Generator produces 5 PWM cycles after triggered. |
011 |
PWM Generator produces 4 PWM cycles after triggered. |
010 |
PWM Generator produces 3 PWM cycles after triggered. |
001 |
PWM Generator produces 2 PWM cycles after triggered. |
000 |
PWM Generator produces 1 PWM cycle after triggered. |
Bit 7 – HREN High-Resolution Enable bit
| Value | Description |
|---|---|
| 1 | Enables fine edge placement module. |
| 0 | Fined edge placement is disabled. |
Bits 4:3 – CLKSEL[1:0] Clock Selection bits(1)
- Do not change the CLKSEL[1:0]
bits while ON (PGxCON[15]) =
1. - The PWM Generator time base operates from the frequency scaling circuit clock, effectively scaling the duty cycle and period of the PWM Generator output.
| Value | Description |
|---|---|
11 |
PWM Generator uses the master clock scaled by the frequency scaling circuit(2). |
10 |
PWM Generator uses the master clock divided by the clock divider circuit(2). |
01 |
PWM Generator uses the master clock selected by the MCLKSEL[1:0] (PCLKCON[1:0]) control bits. |
00 |
No clock selected, PWM Generator is in the lowest power state (default). |
Bits 2:0 – MODSEL[2:0] PWM Generator x Mode Selection bits(1)
| Value | Description |
|---|---|
111 |
Dual Edge Center-Aligned PWM mode (interrupt/register update twice per cycle) |
110 |
Dual Edge Center-Aligned PWM mode (interrupt/register update once per cycle) |
101 |
Double Update Center-Aligned PWM mode |
100 |
Center-Aligned PWM mode |
011 |
LLC Resonant Converter Support PWM mode |
010 |
Independent Edge PWM mode, dual output |
001 |
Variable Phase PWM mode |
000 |
Independent Edge PWM mode |