12.2.29 CAN Receive Interrupt Status Register Low
Note:
- C1RXIFL: FIFO: RFIFx = ‘or’ of enabled RX FIFO flags (flags need to be cleared in the FIFO register).
| Name: | C1RXIFL(1) |
| Offset: | 0x6E0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RFIF[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RFIF[7:1] | |||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 15:8 – RFIF[15:8] Unimplemented
Bits 7:1 – RFIF[7:1] Receive FIFO Interrupt Pending bits
| Value | Description |
|---|---|
1 |
One or more enabled receive FIFO interrupts are pending |
0 |
No enabled receive FIFO interrupts are pending |