12.2.11 CAN2 Mask Register x Low (x = 0 to 15)
| Name: | C2MASKxL |
| Offset: | 0x644, 0x64C, 0x654, 0x65C, 0x664, 0x66C, 0x674, 0x67C, 0x684, 0x68C, 0x694, 0x69C, 0x6A4, 0x6AC, 0x6B4, 0x6BC |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MEID[4:0] | MSID[10:8] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MSID[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:11 – MEID[4:0] Extended Identifier Mask bits
In DeviceNet™ mode, these are the mask bits for the first two data bytes.