12.2.52 CAN Transmit Queue Control Register Low

Legend: HS = Hardware Settable bit; C = Clearable bit

Name: C1TXQCONL
Offset: 0x710

Bit 15141312111098 
      FRESETTXREQUINC 
Access R/WR/WR/W 
Reset 000 
Bit 76543210 
 TXEN  TXATIE TXQEIE TXQNIE 
Access RHS/CR/WR/W 
Reset 0000 

Bit 10 – FRESET FIFO Reset bit

ValueDescription
1

FIFO will be reset when bit is set, cleared by hardware when FIFO is reset; user should poll whether this bit is clear before taking any action
0

No effect

Bit 9 – TXREQ Message Send Request bit

ValueDescription
1

Requests sending a message; the bit will automatically clear when all the messages queued in the TXQ are successfully sent
0

Clearing the bit to ‘0’ while set (‘1’) will request a message abort

Bit 8 – UINC Increment Head/Tail bit

When this bit is set, the FIFO head will increment by a single message.

Bit 7 – TXEN TX Enable bit

Bit 4 – TXATIE Transmit Attempts Exhausted Interrupt Enable bit

ValueDescription
1

Enables interrupt
0

Disables interrupt

Bit 2 – TXQEIE Transmit Queue Empty Interrupt Enable bit

ValueDescription
1

Interrupt is enabled for TXQ empty
0

Interrupt is disabled for TXQ empty

Bit 0 – TXQNIE Transmit Queue Not Full Interrupt Enable bit

ValueDescription
1

Interrupt is enabled for TXQ not full
0

Interrupt is disabled for TXQ not full