12.2.66 CAN Mask Register x Low (x = 0 to 15)
| Name: | C1MASKxL |
| Offset: | 0x784, 0x78C, 0x794, 0x79C, 0x7A4, 0x7AC, 0x7B4, 0x7BC, 0x7C4, 0x7CC, 0x7D4, 0x7DC, 0x7E4, 0x7EC, 0x7F4, 0x7FC |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MEID[4:0] | MSID[10:8] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MSID[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:11 – MEID[4:0] Extended Identifier Mask bits
In DeviceNet™ mode, these are the mask bits for the first two data bytes.