12.2.37 CAN Transmit Request Register Low
Legend: S = Settable bit; HC = Hardware Clearable bit
| Name: | C1TXREQL |
| Offset: | 0x6F0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TXREQ[15:8] | |||||||||
| Access | S/HC | S/HC | S/HC | S/HC | S/HC | S/HC | S/HC | S/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXREQ[7:1] | TXREQ0 | ||||||||
| Access | S/HC | S/HC | S/HC | S/HC | S/HC | S/HC | S/HC | S/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:8 – TXREQ[15:8] Unimplemented
Bits 7:1 – TXREQ[7:1] Message Send Request bits
TXEN = 1 (object configured as a transmit object):
Setting this bit to ‘1’ requests sending a message. The bit will
automatically clear when the message(s) queued in the object is (are) successfully
sent. This bit can NOT be used for aborting a transmission.
TXEN = 0 (object configured as a receive object):
This bit has no effect.
Bit 0 – TXREQ0 Transmit Queue Message Send Request bit
Setting this bit to ‘1’ requests sending a message. The bit
will automatically clear when the message(s) queued in the object is (are)
successfully sent. This bit can NOT be used for aborting a transmission.