12.2.31 CAN Transmit Interrupt Status Register Low
Note:
- C1TXIFL: FIFO: TFIFx = ‘or’ of the enabled TX FIFO flags (flags need to be cleared in the FIFO register).
- TFIF0 is for the Transmit Queue.
| Name: | C1TXIFL(1) |
| Offset: | 0x6E4 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TFIF[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TFIF[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:8 – TFIF[15:8] Unimplemented
Bits 7:0 – TFIF[7:0] Transmit FIFO/TXQ Attempt Interrupt Pending bits(2)
| Value | Description |
|---|---|
1 |
One or more enabled transmit FIFO/TXQ interrupts are pending |
0 |
No enabled transmit FIFO/TXQ interrupts are pending |