12.2.27 CAN Interrupt Register Low

Note:
  1. C1INTL: Flags are set by hardware and cleared by application.

Legend: C = Clearable bit; HS = Hardware Settable bit

Name: C1INTL
Offset: 0x6DC

Bit 15141312111098 
 IVMIFWAKIFCERRIFSERRIFRXOVIFTXATIF   
Access HS/CHS/CHS/CHS/CRR 
Reset 000000 
Bit 76543210 
    TEFIFMODIFTBCIFRXIFTXIF 
Access RHS/CHS/CRR 
Reset 00000 

Bit 15 – IVMIF  Invalid Message Interrupt Flag bit(1)

ValueDescription
1

Invalid message interrupt occurred

0

No invalid message interrupt

Bit 14 – WAKIF  Bus Wake-up Activity Interrupt Flag bit(1)

ValueDescription
1

Wake-up activity interrupt occurred

0

No wake-up activity interrupt

Bit 13 – CERRIF  CAN Bus Error Interrupt Flag bit(1)

ValueDescription
1

CAN bus error interrupt occurred

0

No CAN bus error interrupt

Bit 12 – SERRIF  System Error Interrupt Flag bit(1)

ValueDescription
1

System error interrupt occurred

0

No system error interrupt

Bit 11 – RXOVIF Receive Buffer Overflow Interrupt Flag bit

ValueDescription
1

Receive buffer overflow interrupt occurred

0

No receive buffer overflow interrupt

Bit 10 – TXATIF Transmit Attempt Interrupt Flag bit

ValueDescription
1

Transmit attempt interrupt occurred

0

No transmit attempt interrupt

Bit 4 – TEFIF Transmit Event FIFO Interrupt Flag bit

ValueDescription
1

Transmit event FIFO interrupt occurred

0

No transmit event FIFO interrupt

Bit 3 – MODIF  CAN Mode Change Interrupt Flag bit(1)

ValueDescription
1

CAN module mode change occurred (OPMOD[2:0] have changed to reflect REQOP[2:0])

0

No mode change occurred

Bit 2 – TBCIF  CAN Timer Overflow Interrupt Flag bit(1)

ValueDescription
1

TBC has overflowed

0

TBC has not overflowed

Bit 1 – RXIF Receive Object Interrupt Flag bit

ValueDescription
1

Receive object interrupt is pending

0

No receive object interrupts are pending

Bit 0 – TXIF Transmit Object Interrupt Flag bit

ValueDescription
1

Transmit object interrupt is pending

0

No transmit object interrupts are pending