12.2.26 CAN Interrupt Code Register High
| Name: | C1VECH |
| Offset: | 0x6DA |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RXCODE[6:0] | |||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXCODE[6:0] | |||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 14:8 – RXCODE[6:0] Receive Interrupt Flag Code bits
| Value | Description |
|---|---|
1000001-1111111 |
Reserved |
1000000 |
No interrupt |
0001000-0111111 |
Reserved |
0000111 |
FIFO 7 interrupt (RFIF7 is set) |
| . . . | |
0000010 |
FIFO 2 interrupt (RFIF2 is set) |
0000001 |
FIFO 1 interrupt (RFIF1 is set) |
0000000 |
Reserved; FIFO 0 cannot receive |
Bits 6:0 – TXCODE[6:0] Transmit Interrupt Flag Code bits
| Value | Description |
|---|---|
1000001-1111111 |
Reserved |
1000000 |
No interrupt |
0001000-0111111 |
Reserved |
0000111 |
FIFO 7 interrupt (TFIF7 is set) |
| . . . | |
0000001 |
FIFO 1 interrupt (TFIF1 is set) |
0000000 |
FIFO 0 interrupt (TFIF0 is set) |