12.2.25 CAN Interrupt Code Register Low
| Name: | C1VECL |
| Offset: | 0x6D8 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FILHIT[4:0] | |||||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ICODE[6:0] | |||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 12:8 – FILHIT[4:0] Filter Hit Number bits
| Value | Description |
|---|---|
01111 |
Filter 15 |
01110 |
Filter 14 |
| . . . | |
00001 |
Filter 1 |
00000 |
Filter 0 |
Bits 6:0 – ICODE[6:0] Interrupt Flag Code bits
| Value | Description |
|---|---|
1001011-1111111 |
Reserved |
1001010 |
Transmit attempt interrupt (any bit in C1TXATIF is set) |
1001001 |
Transmit event FIFO interrupt (any bit in C1TEFSTA is set) |
1001000 |
Invalid message occurred (IVMIF/IE) |
1000111 |
CAN module mode change occurred (MODIF/IE) |
1000110 |
CAN timer overflow (TBCIF/IE) |
1000101 |
RX/TX MAB overflow/underflow (RX: Message received before previous message was saved to memory; TX: Can’t feed TX MAB fast enough to transmit consistent data) |
1000100 |
Address error interrupt (illegal FIFO address presented to system) |
1000011 |
Receive FIFO overflow interrupt (any bit in C1RXOVIF is set) |
1000010 |
Wake-up interrupt (WAKIF/WAKIE) |
1000001 |
Error interrupt (CERRIF/IE) |
1000000 |
No interrupt |
0001000-0111111 |
Reserved |
0000111 |
FIFO 7 interrupt (TFIF7 or RFIF7 is set) |
| . . . | |
0000001 |
FIFO 1 interrupt (TFIF1 or RFIF1 is set) |
0000000 |
FIFO 0 interrupt (TFIF0 is set) |