12.2.5 CAN2 FIFO User Address Register x Low (x = 1 to 7)
Note:
- This register is not ensured to read correctly in Configuration mode and should only be accessed when the module is not in Configuration mode.
Legend: x = Bit is unknown
| Name: | C2FIFOUAxL(1) |
| Offset: | 0x5E4, 0x5F0, 0x5FC, 0x608, 0x614, 0x620, 0x62C |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FIFOUA[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | x | x | x | x | x | x | x | x | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FIFOUA[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | x | x | x | x | x | x | x | x | |
Bits 15:0 – FIFOUA[15:0] FIFO User Address bits
TXEN = 1 (FIFO configured as a transmit buffer):
A read of this register will return the address where the next message is to be written (FIFO head).
TXEN = 0 (FIFO configured as a receive buffer):
A read of this register will return the address where the next message is to be read (FIFO tail).