12.2.47 CAN Transmit Event FIFO Status Register
Note:
- These bits are read-only and reflect the status of the FIFO.
Legend: HC = Hardware Clearable bit; S = Settable bit can Set by
‘1’
| Name: | C1TEFSTA |
| Offset: | 0x704 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TEFOVIF | TEFFIF | TEFHIF | TEFNEIF | ||||||
| Access | S/HC | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – TEFOVIF Transmit Event FIFO Overflow Interrupt Flag bit
| Value | Description |
|---|---|
1 |
Overflow event has occurred |
0 |
No overflow event has occurred |
Bit 2 – TEFFIF Transmit Event FIFO Full Interrupt Flag bit(1)
| Value | Description |
|---|---|
1 |
FIFO is full |
0 |
FIFO is not full |
Bit 1 – TEFHIF Transmit Event FIFO Half Full Interrupt Flag bit(1)
| Value | Description |
|---|---|
1 |
FIFO is ≥ half full |
0 |
FIFO is < half full |
Bit 0 – TEFNEIF Transmit Event FIFO Not Empty Interrupt Flag bit(1)
| Value | Description |
|---|---|
1 |
FIFO is not empty |
0 |
FIFO is empty |