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12.2.33 CAN Receive Overflow Interrupt Status Register
Low Note:
C1RXOVIFL: FIFO: RFOVIFx (flag needs to be cleared in the FIFO register).
Name: C1RXOVIFL(1) Offset: 0x6E8
Bit 15 14 13 12 11 10 9 8 RFOVIF[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 RFOVIF[7:1] Access R R R R R R R Reset 0 0 0 0 0 0 0
Bits 15:8 – RFOVIF[15:8] Unimplemented
Bits 7:1 – RFOVIF[7:1] Receive FIFO Overflow
Interrupt Pending bits
Value Description
1
Interrupt is pending
0
Interrupt is not pending
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