12.2.4 CAN2 FIFO Status High Register x (x = 1 to 7)
- FIFOCI[4:0] gives a zero-indexed value to the message in the FIFO. If the FIFO is four messages deep (FSIZE[4:0] = 3), FIFOCIx will take on a value of 0 to 3, depending on the state of the FIFO.
- These bits are updated when a message completes (or aborts) or when the FIFO is reset.
- This bit is reset on any read of this register or when the TXQ is reset. The bits are cleared when TXREQ is set or using an SPI write.
Legend: HS = Hardware Settable bit; C = Clearable bit
| Name: | C2FIFOSTAxH |
| Offset: | 0x5E2, 0x5EE, 0x5FA, 0x608, 0x614, 0x620, 0x62E |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FIFOCI[4:0] | |||||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXABT | TXLARB | TXERR | TXATIF | RXOVIF | TFERFFIF | TFHRFHIF | TFNRFNIF | ||
| Access | R | R | R | HS/C | HS/C | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 12:8 – FIFOCI[4:0] FIFO Message Index bits(1)
TXEN = 1 (FIFO configured as a transmit buffer):
A read of this register will return an index to the message that the FIFO will next attempt to transmit.
TXEN = 0 (FIFO configured as a receive buffer):
A read of this register will return an index to the message that the FIFO will use to save the next message.
Bit 7 – TXABT Message Aborted Status bit(3)
| Value | Description |
|---|---|
1 |
Message was aborted |
0 |
Message completed successfully |
Bit 6 – TXLARB Message Lost Arbitration Status bit(2)
| Value | Description |
|---|---|
1 |
Message lost arbitration while being sent |
0 |
Message did not lose arbitration while being sent |
Bit 5 – TXERR Error Detected During Transmission bit(2)
| Value | Description |
|---|---|
1 |
A bus error occurred while the message was being sent |
0 |
A bus error did not occur while the message was being sent |
Bit 4 – TXATIF Transmit Attempts Exhausted Interrupt Pending bit
TXEN = 0 (FIFO configured as a receive buffer):
Unused, read as ‘0’.
TXEN = 1 (FIFO configured as a transmit buffer):
| Value | Description |
|---|---|
1 |
Interrupt is pending |
0 |
Interrupt is not pending |
Bit 3 – RXOVIF Receive FIFO Overflow Interrupt Flag bit
TXEN = 1 (FIFO configured as a transmit buffer):
Unused, read as ‘0’.
TXEN = 0 (FIFO configured as a receive buffer):
| Value | Description |
|---|---|
1 |
Overflow event has occurred |
0 |
No overflow event has occurred |
Bit 2 – TFERFFIF Transmit/Receive FIFO Empty/Full Interrupt Flag bit
TXEN = 1 (FIFO configured as a transmit FIFO):
Transmit FIFO Empty Interrupt Flag.
1 = FIFO is empty
0 = FIFO is not empty, at least one message is queued to be
transmitted
TXEN = 0 (FIFO configured as a receive FIFO):
Receive FIFO Full Interrupt Flag.
1 = FIFO is full
0 = FIFO is not full
Bit 1 – TFHRFHIF Transmit/Receive FIFO Half Empty/Half Full Interrupt Flag bit
TXEN = 1 (FIFO configured as a transmit FIFO):
Transmit FIFO Half Empty Interrupt Flag.
1 = FIFO is ≤ half full
0 = FIFO is > half full
TXEN = 0 (FIFO configured as a receive FIFO):
Receive FIFO Half Full Interrupt Flag.
1 = FIFO is ≥ half full
0 = FIFO is < half full
Bit 0 – TFNRFNIF Transmit/Receive FIFO Not Full/Not Empty Interrupt Flag bit
TXEN = 1 (FIFO configured as a transmit FIFO):
Transmit FIFO Not Full Interrupt Flag.
1 = FIFO is not full
0 = FIFO is full
TXEN = 0 (FIFO configured as a receive FIFO):
Receive FIFO Not Empty Interrupt Flag.
1 = FIFO is not empty, has at least one message
0 = FIFO is empty