12.2.54 CAN Transmit Queue Status Register
Note:
- The TXQCI[4:0] bits give a zero-indexed value to the message in the TXQ. If the TXQ is four messages deep (FSIZE[4:0] = 3), TXQCIx will take on a value of 0 to 3, depending on the state of the TXQ.
- This bit is updated when a message completes (or aborts) or when the TXQ is reset.
Legend: HS = Hardware Settable bit; C = Clearable bit
| Name: | C1TXQSTAL |
| Offset: | 0x714 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TXQCI[4:0] | |||||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXABT | TXLARB | TXERR | TXATIF | TXQEIF | TXQNIF | ||||
| Access | R | R | R | HS/C | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 1 | 1 |
Bits 12:8 – TXQCI[4:0] Transmit Message Queue Index bits(1)
A read of this register will return an index to the message that the FIFO will next attempt to transmit.
Bit 7 – TXABT Message Aborted Status bit(2)
| Value | Description |
|---|---|
1 |
Message was aborted |
0 |
Message completed successfully |
Bit 6 – TXLARB Message Lost Arbitration Status bit
| Value | Description |
|---|---|
1 |
Message lost arbitration while being sent |
0 |
Message did not lose arbitration while being sent |
Bit 5 – TXERR Error Detected During Transmission bit
| Value | Description |
|---|---|
1 |
A bus error occurred while the message was being sent |
0 |
A bus error did not occur while the message was being sent |
Bit 4 – TXATIF Transmit Attempts Exhausted Interrupt Pending bit
| Value | Description |
|---|---|
1 |
Interrupt is pending |
0 |
Interrupt is not pending |
Bit 2 – TXQEIF Transmit Queue Empty Interrupt Flag bit
| Value | Description |
|---|---|
1 |
TXQ is empty |
0 |
TXQ is not empty, at least one message is queued to be transmitted |
Bit 0 – TXQNIF Transmit Queue Not Full Interrupt Flag bit
| Value | Description |
|---|---|
1 |
TXQ is not full |
0 |
TXQ is full |