5.8.4 ECS

The ECS bit is the ECC Correction Signal control bit. It is a volatile writable bit configured using the 56H command. When ECC is enabled (ECC = 1), the hardware /ECS pin is used by the system to detect ECC events during read operations. When ECS = 0, the /ECS pin is driven low during the aligned 16-byte data output period if a SEC (Single Error Correction) event occurs within the corresponding 16-byte ECC granularity. When ECS = 1, the /ECS pin is driven low when a DED (Double Error Detection) event occurs. When ECC is disabled (ECC = 0), the ECS bit is ignored and the /ECS pin is disabled.