5.8.3 DLP

The DLP bit is the Data Learning Pattern Enable bit. It is a volatile writable bit configured using the 56H command. For Quad Output, Quad I/O and Quad I/O DTR Fast Read commands, a predefined Data Learning Pattern can be used by the Flash memory controller to determine the optimal Flash data output timing on the four I/O pins. When DLP = 1, beginning with the third dummy clock cycle, the Flash outputs the ‘00110100’ Data Learning Pattern sequence on each of the four I/O pins. During this period, the controller can fine-tune the data latching timing for each I/O pin to optimize system performance. When DLP = 0, the Data Learning Pattern output is disabled.