11.3.3 Tri-State Enable Register
Note: See pinout diagrams for I/0 availability for a given
device.
| Name: | TRISx |
| Offset: | 0x0208, 0x021C, 0x0230, 0x0244, 0x0258, 0x026C, 0x0280, 0x0294 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TRISx[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRISx[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
Bits 15:0 – TRISx[15:0] Tri-State Enable bits
| Value | Description |
|---|---|
1 |
I/O is tri-stated. |
0 |
I/O is driven with LATx register bit value. |