11.3.72 IOIM x Control Register

Name:	IOIMxCON
Offset:	0x1E90, 0x1E9C, 0x1EA8, 0x1EB4, 0x1EC0, 0x1ECC, 0x1ED8, 0x1EE4, 0x1EF0, 0x1EFC, 0x1F08, 0x1F14, 0x1F20, 0x1F2C, 0x1F38, 0x1F44


Bit	31	30	29	28	27	26	25	24
					FLTINJ	OKINJ	ATEST[1:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	23	22	21	20	19	18	17	16
	EOVFV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ON		SLPEN	SIDL		EXTCLK
Access	R/W		R/W	R/W		R/W
Reset	0		0	0		0


Bit	7	6	5	4	3	2	1	0
	FBKSEL[3:0]				REFSEL[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 27 – FLTINJ Fault Injection bit

A write of ‘1’ to this bit will simulate a comparison mismatch event. The ERR bit will become set, the ERRCNT will increment to EOVFV and the OVF will become set if the ERRCNT overflows.

Bit 26 – OKINJ OK Inject bit

A write of ‘1’ to this bit will simulate a transition on the reference signal input, blanking time insertion and a good comparison between reference and feedback signals. The OK bit will become set.

Bits 25:24 – ATEST[1:0] Artificial Test Enable bits

Value	Description
11	Artificial OKINJ Test is enabled.
10	Artificial FLTINJ Test is enabled.
01	Artificial Test disabled.
00	Artificial Test disabled.

Bits 23:16 – EOVFV[7:0] Error-Counter Overflow Value bits

Bit 15 – ON Module Enable bit

Value	Description
1	IOIM module is enabled.
0	IOIM module is disabled.

Bit 13 – SLPEN Module Sleep Enable bit

Value	Description
1	Module operates in Sleep mode.
0	Module disabled in Sleep mode.

Bit 12 – SIDL Module Stop in Idle Mode Enable bit

Value	Description
1	Module disabled in Idle mode.
0	Module operates in Idle mode.

Bit 10 – EXTCLK External Clock Source Enable bit

Value	Description
1	CLKGEN13 (200 MHz)
0	T_CY (Instruction Cycle) (default)

Bits 7:4 – FBKSEL[3:0] Feedback Input Mux Selection bits

For IOIM Group A, see Table 11-22.

For IOIM Group B, see Table 11-24.

Value	Description
1111	Feedback input [15] is selected.
...
0001	Feedback input [1] is selected.
0000	Feedback input [0] is selected.

Bits 3:0 – REFSEL[3:0] Reference Input Mux Selection bits

Value	Description
1111	Reference input [15] is selected.
...
0001	Reference input [1] is selected.
0000	Reference input [0] is selected.