18.4.52 DDR3PHY Word Error Register

Name:	DDR3PHY_BISTWER
Offset:	0x128
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	DXWER[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DXWER[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ACWER[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ACWER[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:16 – DXWER[15:0] Byte Word Error

Indicates the number of word errors on the byte lane. An error on any bit of the data bus including the data mask bit increments the error count.

Bits 15:0 – ACWER[15:0] Address/Command Word Error

Indicates the number of word errors on the address/command lane. An error on any bit of the address/command bus increments the error count.

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