18.4.48 DDR3PHY BIST Address 1 Register

Name:	DDR3PHY_BISTAR1
Offset:	0x118
Reset:	0x0000000C
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	BAINC[11:4]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	BAINC[3:0]				BMRANK[1:0]		BRANK[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	1	1	0	0

Bits 15:4 – BAINC[11:0] BIST Address Increment

Selects the value by which the SDRAM address is incremented for each write/read access. This value must be at the beginning of a burst boundary, i.e. the lower bits must be “0000” for BL16, “000” for BL8, “00” for BL4 and “0” for BL2.

Bits 3:2 – BMRANK[1:0] BIST Maximum Rank

Maximum SDRAM rank to be used during BIST. Write to 0 (only one rank).

Bits 1:0 – BRANK[1:0] BIST Rank

SDRAM rank to be used during BIST. Write to 0 (only one rank).