18.4.21 DDR3PHY Mode Register 1 (MR1) (LPDDR3 Mode)

Name:	DDR3PHY_MR1_LPDDR3
Offset:	0x44
Reset:	0x00000002
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	nWR[2:0]					BL[2:0]
Access	R/W	R/W	R/W			R/W	R/W	R/W
Reset	0	0	0			0	1	0

Bits 7:5 – nWR[2:0] Write Recovery

Valid values are as follows. All other settings are reserved and must not be used.

Value	Description
	If nWRE (MR2 [4]) = 0:
1	nWR=3
4	nWR=6
6	nWR=8
7	nWR=9
	If nWRE (MR2[4]) = 1:
0	nWR=10
1	nWR=11
2	nWR=12

Bits 2:0 – BL[2:0] Burst Length

Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are: 011 = 8 All other settings are reserved and must not be used.