18.4.30 DDR3PHY ODT Configuration Register
| Name: | DDR3PHY_ODTCR |
| Offset: | 0x50 |
| Reset: | 0x00010000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WRODT0 | |||||||||
| Access | R/W | ||||||||
| Reset | 1 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RDODT0 | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 16 – WRODT0 Write ODT
Bit 0 – RDODT0 Read ODT
Note: RODT0 is applicable to DDR2 only.