18.4.24 DDR3PHY Mode Register 2 (MR2/EMR2) (LPDDR2 Mode)

Name:	DDR3PHY_MR2_LPDDR2
Offset:	0x48
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	RSVD[3:0]				RL/WL[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:4 – RSVD[3:0] Reserved

These are JEDEC reserved bits and are recommended by JEDEC to be programmed to ‘0’

Bits 3:0 – RL/WL[3:0] Read and Write Latency

Valid values are as follows. All other settings are reserved and must not be used.

Value	Description
1	RL = 3 / WL = 1
2	RL = 4 / WL = 2
3	RL = 5 / WL = 2
4	RL = 6 / WL = 3
5	RL = 7 / WL = 4
6	RL = 8 / WL = 4

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.