18.4.47 DDR3PHY BIST Address 0 Register

Name:	DDR3PHY_BISTAR0
Offset:	0x114
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
		BBANK[2:0]			BROW[15:12]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	BROW[11:4]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	BROW[3:0]				BCOL[11:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	BCOL[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 30:28 – BBANK[2:0] BIST Bank Address

Selects the SDRAM bank address to be used during BIST.

Bits 27:12 – BROW[15:0] BIST Row Address

Selects the SDRAM row address to be used during BIST.

Bits 11:0 – BCOL[11:0] BIST Column Address

Selects the SDRAM column address to be used during BIST. The lower bits of this address must be “0000” for BL16, “000” for BL8, “00” for BL4 and “0” for BL2.