18.4.31 DDR3PHY Data Training Address Register

Name:	DDR3PHY_DTAR
Offset:	0x54
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	DTMPR	DTBANK[2:0]			DTROW[15:12]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DTROW[11:4]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	DTROW[3:0]				DTCOL[11:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DTCOL[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 31 – DTMPR Data Training Using MPR (DDR3 Only)

If set, specifies that data training must use the DDR3 Multi-Purpose register (MPR) register. Otherwise data training is performed by first writing to some locations in the SDRAM and then reading them back.

Bits 30:28 – DTBANK[2:0] Data Training Bank Address

Selects the SDRAM bank address to be used during data training.

Bits 27:12 – DTROW[15:0] Data Training Row Address

Selects the SDRAM row address to be used during data training.

Bits 11:0 – DTCOL[11:0] Data Training Column Address

Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “0000”.