18.4.28 DDR3PHY Mode Register 3 (MR3) (LPDDR2 Mode)

Name:	DDR3PHY_MR3_LPDDR2
Offset:	0x4C
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	RSVD[3:0]				DS[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:4 – RSVD[3:0] Reserved

These are JEDEC reserved bits and are recommended by JEDEC to be programmed to ‘0’.

Bits 3:0 – DS[3:0] Drive Strength

Valid values are as follows. All other settings are reserved and must not be used.

Value	Description
0	Reserved
1	34.3-ohm typical
2	40-ohm typical
3	48-ohm typical
4	60-ohm typical
5	Reserved
6	80-ohm typical
7	120-ohm typical

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.