18.4.54 DDR3PHY BIST Bit Error 1 Register

Name:	DDR3PHY_BISTBER1
Offset:	0x130
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
							ODTBER[1:0]
Access							R/W	R/W
Reset							0	0


Bit	23	22	21	20	19	18	17	16
							CSBER[1:0]
Access							R/W	R/W
Reset							0	0


Bit	15	14	13	12	11	10	9	8
							CKEBER[1:0]
Access							R/W	R/W
Reset							0	0


Bit	7	6	5	4	3	2	1	0
	WEBER[1:0]		BABER[5:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 25:24 – ODTBER[1:0] DDR_ODT Bit Error

Bit error count on DDR_ODT.

Bits 17:16 – CSBER[1:0] DDR_CSN Bit Error

Bit error count on DDR_CSN.

Bits 9:8 – CKEBER[1:0] DDR_CKE Bit Error

Bit error count on DDR_CKE.

Bits 7:6 – WEBER[1:0] DDR_WEN Bit Error

Bit error count on DDR_WEN.

Bits 5:0 – BABER[5:0] Bank Address Bit Error

Each group of two bits indicates the bit error count on each DDR_BA[2:0]. BABER[1:0] is the error count for DDR_BA[0], BABER[3:2] for DDR_BA[1], and so on.