18.4.2 DDR3PHY PHY General Configuration Register


Bit	31	30	29	28	27	26	25	24
	LBMODE	LBGDQS	LBDQSS					PDDISDX
Access	R/W	R/W	R/W					R/W
Reset	0	0	0					1


Bit	23	22	21	20	19	18	17	16
	ZCKSEL[1:0]					RANKEN
Access	R/W	R/W				R/W
Reset	1	0				1


Bit	15	14	13	12	11	10	9	8
	IOLB	CKINV	CKDV[1:0]				CKEN
Access	R/W	R/W	R/W	R/W			R/W
Reset	0	0	1	0			1


Bit	7	6	5	4	3	2	1	0
				DFTLMT[1:0]		DFTCMP	DQSCFG	ITMDMD
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	1	0	0

Bit 31 – LBMODE Loopback Mode

If set, indicates that the DDR3PHY is in Loopback mode.

Bit 30 – LBGDQS Loopback DDR_DQS Gating

Selects the DDR_DQS gating mode that must be used when the DDR3PHY is in Loopback mode, including BIST Loopback mode.

Note: When LBGDQS=0, DDR3PHY_PIR.QSTRN must not be run prior to running BIST loopback.

Value	Description
0	DDR_DQS gate is set by the DDR_DQS gate training.
1	DDR_DQS gate is set manually using software.

Bit 29 – LBDQSS Loopback DDR_DQS Shift

Selects how the read DDR_DQS is shifted during loopback to ensure that the read DDR_DQS is centered into the read data eye.

Value	Description
0	DDR3PHY sets the read DDR_DQS delay to 0, DDR_DQS is already shifted 90 degrees by write path.
1	The read DDR_DQS shift is set manually through software.

Bit 24 – PDDISDX Power Down Disabled Byte

If set, indicates that the DLL and I/Os of a disabled byte must be powered down.

Bits 23:22 – ZCKSEL[1:0] Impedance Clock Divider Select

Selects the divide ratio for the clock used by the impedance control logic, the frequency must be inferior to 25 MHz. The source clock for the divider is PLLDDR/4.

Value	Description
0	Divide by 2
1	Divide by 8
2	Divide by 32
3	Divide by 64

Bit 18 – RANKEN Rank Enable

Must be written to '1'.

Bit 15 – IOLB I/O Loopback Select

Selects where the signal loopback occurs inside the I/O.

Value	Description
0	Loopback is after output buffer; output enable must be asserted.
1	Loopback is before output buffer; output enable is don’t care.

Bit 14 – CKINV DDR_CLK Invert

If set, inverts the DDR_CLK/DDR_CLKN polarity. Otherwise DDR_CLK/DDR_CLKN toggle with normal polarity.

Bits 13:12 – CKDV[1:0] DDR_CLK Disable Value

Specifies the static value that must be driven on DDR_CLK/DDR_CLKN when disabled. CKDV[0] specifies the value for DDR_CLK and CKDV[1] specifies the value for DDR_CLKN.

Bit 9 – CKEN DDR_CLK Enable

Controls whether DDR_CLK going to the SDRAM is enabled (toggling) or disabled (static value defined by CKDV).

Bits 4:3 – DFTLMT[1:0] DDR_DQS Drift Limit

A drift of this value or greater is reported as a drift error through the host port error flag.

Note: Although reported through the error flag, DFTLMT indicates only that the drift is greater than expected. This error does not require any action.

Value	Description
0	No limit of drift on read data strobes(no error reported)
1	90° drift
2	180° drift
3	270° or more drift

Bit 2 – DFTCMP DDR_DQS Drift Compensation

Drift compensation is not supported in the following situations:

- LPDDR2/3 (DDR3PHY_DCR.DDRMD set to LPDDR2)

- Burst length 2 (DDR3PHY_MR0.BL set to burst length of 2)

- Read DDR_DQS gating using passive windowing (DQSCFG set to passive windowing)

Drift compensation must be set to disabled if any of the above are set.

Value	Description
0	Disables data strobe drift compensation.
1	Enables data strobe drift compensation.Defalut value.

Bit 1 – DQSCFG DDR_DQS Gating Configuration

Note: Passive windowing must be used for LPDDR2/3.

Value	Description
0	DDR_DQS gating is shut off using the rising edge of DDR_DQSN (Active Windowing mode).
1	DDR_DQS gating blankets the whole burst (Passive Windowing mode).

Bit 0 – ITMDMD ITM DDR Mode

Note: The correct setting when using DDR is 1 because DDR_DQSN is not used by DDR.

Value	Description
0	ITMS uses DDR_DQS and DDR_DQSN.
1	ITMS uses DDR_DQS only.

Name:	DDR3PHY_PGCR
Offset:	0x08
Reset:	0x01842E04
Property:	Read/Write