18.4.18 DDR3PHY Mode Register 1 (MR1) (DDR3 Mode)


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
				QOFF	TDQS		RTT2
Access				R/W	R/W		R/W
Reset				0	0		0


Bit	7	6	5	4	3	2	1	0
	LEVEL	RTT1	DIC1	AL[1:0]		RTT0	DIC0	DE
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 12 – QOFF Output Enable/Disable

When ‘0’, all outputs function normally; when ‘1’, all SDRAM outputs are disabled, removing output buffer current. This feature is used for IDD characterization of read current and must not be used in normal operation.

Bit 11 – TDQS Termination Data Strobe

When enabled (‘1’), TDQS provides additional termination resistance outputs that may be useful in some system configurations. Refer to the SDRAM memory device data sheet for details.

Bit 9 – RTT2 On-Die Termination

Selects the resistance for SDRAM on-die termination. For all bits RTTx, valid values are as follows. All other settings are reserved and must not be used.

Value	Description
0	ODT disabled
1	R_ZQ/4
2	R_ZQ/2
3	R_ZQ/6
4	R_ZQ/12
5	R_ZQ/8

Bit 7 – LEVEL Write Leveling Enable

Enables write-leveling when set.

Bit 6 – RTT1 On-Die Termination

Selects the resistance for SDRAM on-die termination. See RTT2.

Bit 5 – DIC1 Output Driver Impedance Control

Controls the output drive strength. For all bits DICx, valid values are as follows.

Value	Description
0	R_ZQ/6
1	R_ZQ/7
2	Reserved
3	Reserved

Bits 4:3 – AL[1:0] Posted CAS Additive Latency

Setting additive latency that allows read and write commands to be issued to the SDRAM earlier than normal (refer to the SDRAM memory device data sheet for details).

Value	Description
0	0 (AL disabled)
1	CL - 1
2	CL - 2
3	Reserved

Bit 2 – RTT0 On-Die Termination

Selects the effective resistance for SDRAM on-die termination. See RTT2.

Bit 1 – DIC0 Output Driver Impedance Control

See DIC1.

Bit 0 – DE DLL Enable/Disable

DLL must be enabled for normal operation.

Value	Description
0	Enable the DLL
1	Disable the DLL

Name:	DDR3PHY_MR1_DDR3
Offset:	0x44
Reset:	0x00000000
Property:	Read/Write