18.4.66 DDR3PHY Data Byte DLL Control Register

A disabled DLL is bypassed. Default ('0') is DLL enabled.

Soft resets the byte DLL by driving the DLL soft reset pin.

If this bit is set, the client DLL is put in Loopback mode in which there is no 90 degrees phase shift on read DDR_DQS/DDR_DQSN. This bit must be set when operating the byte PHYs in Loopback mode such as during BIST loopback.

Enables the analog test signal to be output on the DLL analog test output (test_out_a). The DLL analog test output is tri-stated when this bit is '0'.

Selects the phase difference between the input clock and the corresponding output clock of the client DLL.

Value	Description
0	90
1	72
2	54
3	36
4	108
5	90
6	72
7	54
8	126
9	108
10	90
11	72
12	144
13	126
14	108
15	90

Used to control how the client DLL starts up relative to the host DLL locking.

Value	Description
0–1	Client DLL automatically starts up once the host DLL has achieved lock.
2	The automatic start-up of the client DLL is disabled; the phase detector is disabled.
3	The automatic start-up of the client DLL is disabled; the phase detector is enabled.

Used to trim the delay in the host DLL feed-forward path.

Value	Description
0	Minimum delay
1–6	Valid values, within range
7	Maximum delay

Used to trim the delay in the host DLL feedback path.

Value	Description
0	Minimum delay
1–6	Valid values, within range
7	Maximum delay

Used to trim the delay in the client DLL feed-forward path.

Value	Description
0	Minimum delay
1–6	Valid values, within range
7	Maximum delay

Used to trim the delay in the client DLL feedback path.

Value	Description
0	Minimum delay
1–6	Valid values, within range
7	Maximum delay