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18.4.45 DDR3PHY BIST Mask 1
Register Name: DDR3PHY_BISTMSKR1 Offset: 0x108 Reset: 0x00000000 Property: Read/Write
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 CASMSK RASMSK DMMSK[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 Access Reset
Bit 7 6 5 4 3 2 1 0 DQMSK[1:0] Access R/W R/W Reset 0 0
Bit 19 – CASMSK DDR_CASN Mask Bit
Bit 18 – RASMSK DDR_RASN Mask Bit
Bits 17:16 – DMMSK[1:0] DDR_DQM Mask Bit
Bits 1:0 – DQMSK[1:0] DDR_D Mask Bit
Mask
bit for each DDR_D[7:0] bit.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
