18.4.20 DDR3PHY Mode Register 1 (MR1) (LPDDR2 Mode)

Name:	DDR3PHY_MR1_LPDDR2
Offset:	0x44
Reset:	0x00000002
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	nWR[2:0]			WC	BT	BL[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	1	0

Bits 7:5 – nWR[2:0] Write Recovery

Valid values are as follows. All other settings are reserved and must not be used.

Value	Description
0	reserved
1	3 cycles
2	4 cycles
3	5 cycles
4	6 cycles
5	7 cycles
6	8 cycles

Bit 4 – WC Wrap Control

Value	Description
0	Wrap
1	No wrap

Bit 3 – BT Burst Type

Indicates whether a burst is sequential or interleaved.

Value	Description
0	Sequential burst
1	Interleaved burst

Bits 2:0 – BL[2:0] Burst Length

Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are as follows. All other settings are reserved and must not be used.

Value	Description
2	4
3	8
4	16