18.4.55 DDR3PHY BIST Bit Error 2 Register

Name:	DDR3PHY_BISTBER2
Offset:	0x134
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	DQBER[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DQBER[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	DQBER[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DQBER[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – DQBER[31:0] Data Bit Error

The first 16 bits indicate the error count for the first data beat (i.e. the data driven out on DDR_D[7:0] on the rising edge of DDR_DQS). The second 16 bits indicate the error on the second data beat (i.e. the error count of the data driven out on DDR_D[7:0] on the falling edge of DDR_DQS). For each of the 16-bit group, the first 2 bits are for DDR_D0, the second for DDR_D1, and so on.