18.4.36 DDR3PHY DCU Run Register


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	XCEN	RCEN	SCOF	SONF	NFAIL[7:4]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	NFAIL[3:0]				EADDR[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SADDR[3:0]				DINST[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 23 – XCEN Expected Compare Enable

If set, indicates that read data coming back from the SDRAM is compared with the expected data.

Bit 22 – RCEN Read Capture Enable

If set, indicates that read data coming back from the SDRAM is captured into the read data cache.

Bit 21 – SCOF Stop Capture On Full

If set, specifies that the capture of read data stops when the capture cache is full.

Bit 20 – SONF Stop On Nth Fail

If set, specifies that the execution of commands and the capture of read data stop when there are N read data failures. The number of failures is specified by NFAIL. Otherwise commands execute until the end of the program or until manually stopped using a STOP command.

Bits 19:12 – NFAIL[7:0] Number of Failures

Specifies the number of failures after which the execution of commands and the capture of read data stop if SONF is set. Execution of commands and the capture of read data stop after (NFAIL+1) failures if SONF is set.

Bits 11:8 – EADDR[3:0] End Address

Cache word address where the execution of commands ends.

Bits 7:4 – SADDR[3:0] Start Address

Cache word address where the execution of commands begins.

Bits 3:0 – DINST[3:0] DCU Instruction

Selects the DCU command to be executed.

Value	Description
0	NOP: No operation
1	Run: Triggers the execution of commands in the command cache
2	Stop: Stops the execution of commands in the command cache.
3	Stop Loop: Stops the execution of an infinite loop in the command cache.
4	Reset: Resets all DCU run time registers
5–7	Reserved

Name:	DDR3PHY_DCURR
Offset:	0xC8
Reset:	0x00000000
Property:	Read/Write