18.4.58 DDR3PHY Fail Word 1 Register

Name:	DDR3PHY_BISTFWR1
Offset:	0x140
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					CASWEBS	RASWEBS	DMWEBS[1:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
	DQWEBS[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DQWEBS[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 19 – CASWEBS DDR_CASN Word Error Bit Status

Bit status during a word error for DDR_CASN.

Bit 18 – RASWEBS DDR_RASN Word Error Bit Status

Bit status during a word error for DDR_RASN.

Bits 17:16 – DMWEBS[1:0] DDR_DQM Word Error Bit Status

Bit status during a word error for DDR_DQM. DMWEBS[0] is for the first DDR_DQM beat, and DMWEBS[1] is for the second DDR_DQM beat.

Bits 15:0 – DQWEBS[15:0] DDR_D Word Error Bit Status

Bit status during a word error for each DDR_D[7:0]. The first 8 bits indicate the status of the first data beat (i.e. the status of the data driven out on DDR_D[7:0] on the rising edge of DDR_DQS). The second 8 bits indicate the status of the second data beat (i.e. the status of the data driven out on DDR_D[7:0] on the falling edge of DDR_DQS). For each of the 8-bit group, the first bit is for DDR_D0, the second bit is for DDR_D1, and so on.