18.4.9 DDR3PHY AC I/O Configuration Register
| Name: | DDR3PHY_ACIOCR |
| Offset: | 0x24 |
| Reset: | 0x30400812 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | RSTIOM | RSTPDR | RSTPDD | RSTODT | | | |
| Access | | | R/W | R/W | R/W | R/W | | | |
| Reset | | | 1 | 1 | 0 | 0 | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | RANKPDR | | | | CSPDD | | | |
| Access | | R/W | | | | R/W | | | |
| Reset | | 1 | | | | 0 | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | RANKODT | | | CKPDR | | | CKPDD | |
| Access | | R/W | | | R/W | | | R/W | |
| Reset | | 0 | | | 1 | | | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | CKODT | ACPDR | ACPDD | ACODT | ACOE | ACIOM | |
| Access | | | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | | | 0 | 1 | 0 | 0 | 1 | 0 | |
Bit 29 – RSTIOM SDRAM Reset I/O Mode
Bit 28 – RSTPDR SDRAM Reset Power-Down
Receiver
When set, powers down the input
receiver on the I/O for DDR_RESETN.
Bit 27 – RSTPDD SDRAM Reset Power-Down
Driver
When set, powers down the output
driver on the I/O for DDR_RESETN.
Bit 26 – RSTODT SDRAM Reset On-Die Termination
When set, enables the on-die
termination on the I/O for DDR_RESETN.
Bit 22 – RANKPDR Rank Power-Down
Receiver
When set, powers down the input
receiver on the I/O DDR_CKE, DDR_ODT, and DDR_CSN pins.
Bit 18 – CSPDD DDR_CSN Power Down
Driver
When set, powers down the output
driver on the I/O for DDR_CSN pins. DDR_CKE and DDR_ODT driver power-down is controlled by
DDR3PHY_DSGCR.
Bit 14 – RANKODT Rank On-Die Termination
When set, enables the on-die
termination on the I/O for DDR_CKE, DDR_ODT, and DDR_CSN pins.
Bit 11 – CKPDR DDR_CLK Power Down
Receiver
When set, powers down the input
receiver on the I/O for DDR_CLK.
Bit 8 – CKPDD DDR_CLK Power Down
Driver
When set, powers down the output
driver on the I/O for DDR_CLK.
Bit 5 – CKODT DDR_CLK On-Die
Termination
When set, enables the on-die
termination on the I/O for DDR_CLK.
Bit 4 – ACPDR AC Power-Down
Receiver
When set, powers down the input
receiver on the I/O for DDR_RASN, DDR_CASN, DDR_WEN, DDR_BA[2:0], and DDR_A[15:0]
pins.
Bit 3 – ACPDD AC Power-Down
Driver
When set, powers down the output
driver on the I/O for DDR_RASN, DDR_CASN, DDR_WEN, DDR_BA[2:0], and DDR_A[15:0]
pins.
Bit 2 – ACODT Address/Command On-Die Termination
When set, enables the on-die
termination on the I/O for DDR_RASN, DDR_CASN, DDR_WEN, DDR_BA[2:0], and DDR_A[15:0]
pins.
Bit 1 – ACOE Address/Command Output Enable
When set, enables the output
driver on the I/O for all address and command pins.
Bit 0 – ACIOM Address/Command I/O Mode
