18.4.34 DDR3PHY DCU Address Register

Name:	DDR3PHY_DCUAR
Offset:	0xC0
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
					ATYPE	INCA	CSEL[1:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CSADDR[3:0]				CWADDR[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 11 – ATYPE Access Type

Specifies the type of access to be performed using this address.

Value	Description
0	Write access
1	Read access

Bit 10 – INCA Increment Address

If set, specifies that the cache address specified in CWADDR and CSADDR are automatically incremented after each access of the cache. The increment happens in such a way that all the slices of a selected word are first accessed before going to the next word.

Bits 9:8 – CSEL[1:0] Cache Select

Selects the cache to be accessed.

Value	Description
0	Command cache
1	Expected data cache
2	Read data cache
3	Reserved

Bits 7:4 – CSADDR[3:0] Cache Slice Address

Address of the cache slice to be accessed.

Bits 3:0 – CWADDR[3:0] Cache Word Address

Address of the cache word to be accessed.