18.4.11 DDR3PHY DDR System General Configuration Register


Bit	31	30	29	28	27	26	25	24
	CKEOE	RSTOE	ODTOE	CKOE			NL2OE	NL2PD
Access	R/W	R/W	R/W	R/W			R/W	R/W
Reset	1	1	1	1			1	0


Bit	23	22	21	20	19	18	17	16
				ODTPDD				CKEPDD
Access				R/W				R/W
Reset				0				0


Bit	15	14	13	12	11	10	9	8
				FXDLAT	NOBUB	DQSGE[2:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DQSGX[2:0]			LPDLLPD	LPIOPD	ZUEN	BDISEN	PUREN
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	1	1	1	1	1

Bit 31 – CKEOE DDR_CKE Output Enable

When set, enables the output driver on the I/O for DDR_CKE.

Bit 30 – RSTOE DDR_RESETN Output Enable

When set, enables the output driver on the I/O for DDR_RESETN.

Bit 29 – ODTOE DDR_ODT Output Enable

When set, enables the output driver on the I/O for DDR_ODT.

Bit 28 – CKOE DDR_CLK Output Enable

When set, enables the output driver on the I/O for DDR_CLK/DDR_CLKN.

Bit 25 – NL2OE Non-LPDDR2/LPDDR3 Output Enable

When set, enables the output driver on the I/O for non-LPDDR2/LPDDR3 (DDR_ODT, DDR_RASN, DDR_CASN, DDR_WEN, and DDR_BA) pins. This may be used when a chip that is designed for both LPDDR2/LPDDR3 and other DDR modes is being used in LPDDR2/LPDDR3 mode. For these pins, the I/O output enable signal (OE) is an AND of this bit and the respective output enable bit in DDR3PHY_ACIOCR or DDR3PHY_DSGCR registers.

Bit 24 – NL2PD Non-LPDDR2/LPDDR3 Power-Down

When set, powers down the output driver and the input receiver on the I/O for non-LPDDR2/LPDDR3 (DDR_ODT, DDR_RASN, DDR_CASN, DDR_WEN, and DDR_BA) pins. This may be used when a chip that is designed for both LPDDR2/LPDDR3 and other DDR modes is being used in LPDDR2/LPDDR3 mode.

Bit 20 – ODTPDD DDR_ODT Power-Down Driver

When set, powers down the output driver on the I/O for DDR_ODT.

Bit 16 – CKEPDD DDR_CKE Power-Down Driver

When set, powers down the output driver on the I/O for DDR_CKE.

Bit 12 – FXDLAT Fixed Latency

Specifies whether all reads must be returned to the controller with a fixed read latency.

Either NOBUB or FXDLAT must be set to 1.

Value	Description
0	Disables fixed read latency.
1	Enables fixed read latency.

Bit 11 – NOBUB No Bubbles

Specifies whether reads must be returned to the controller with no bubbles.

Either NOBUB or FXDLAT must be set to 1.

Value	Description
0	Bubbles are allowed during reads
1	Bubbles are not allowed during reads

Bits 10:8 – DQSGE[2:0] DDR_DQS Gate Early

Specifies the number of clock cycles for which the DDR_DQS gating must be enabled earlier than its normal position. Only applicable when using passive DDR_DQS gating and no drift compensation. This field is recommended to be set to zero for all DDR types other than LPDDR2/LPDDR3. For LPDDR2/LPDDR3 it must be set to (t_DQSCKmax - t_DQSCKmin) divided by clock period and rounded up. t_DQSCKmax and t_DQSCKmin can be found in the LPDDR2 vendor datasheet.

Bits 7:5 – DQSGX[2:0] DDR_DQS Gate Extension

Specifies the number of clock cycles for which the DDR_DQS gating must be extended beyond the normal burst length width. Only applicable when using passive DDR_DQS gating and no drift compensation. This field is recommended to be set to zero for all DDR types other than LPDDR2/LPDDR3. For LPDDR2/LPDDR3, it must be set to (t_DQSCKmax - t_DQSCKmin), divided by clock period and rounded up. t_DQSCKmax and t_DQSCKmin can be found in the LPDDR2 vendor datasheet.

Bit 4 – LPDLLPD Low-Power DLL Power Down

If set, specifies that the PHY responds to the DFI low-power opportunity request and powers down the DLL of the PHY if the wakeup time request satisfies the DLL lock time.

Bit 3 – LPIOPD Low-Power I/O Power Down

If set, specifies that the PHY responds to the DFI low-power opportunity request and powers down the I/Os of the PHY.

Bit 2 – ZUEN Impedance Update Enable

If set, specifies that the PHY performs impedance calibration (update) whenever there is a controller-initiated DFI update request. Otherwise the PHY ignores an update request from the controller.

Bit 1 – BDISEN Byte Disable Enable

If set, specifies that the PHY responds to DFI byte disable request. Otherwise the byte disable from the DFI is ignored, in which case bytes can only be disabled using DDR3PHY_DXnGCR.

Bit 0 – PUREN PHY Update Request Enable

If set, specifies that the PHY issues PHY-initiated DFI update requests when there is DDR_DQS drift of more than ¾ of a clock cycle within one continuous (back-to-back) read burst. By default, the PHY issues PHY-initiated update requests and the controller must respond, otherwise the PHY may return erroneous values. The option to disable it is provided only for silicon evaluation and testing.

Name:	DDR3PHY_DSGCR
Offset:	0x2C
Reset:	0xFA00001F
Property:	Read/Write